Research

Structured applied research in verification, test, reliability and AI-driven engineering systems.

SIS conducts research to anticipate structural inflection points in semiconductor engineering — from scalable verification architectures and advanced 3DIC methodologies to memory test, repair strategies, reliability modeling, and AI-augmented engineering systems. Research bridges formal rigor and industrial deployment, ensuring innovation remains grounded in real system constraints.

Research Positioning

Research at SIS is structured around three principles:

  • ▹Methodological rigor— formal foundations, reproducibility, standards alignment and peer validation.
  • ▹Industrial relevance— direct applicability to verification, DFT, test and reliability environments.
  • ▹Architectural foresight— anticipating complexity growth in heterogeneous, chiplet-based and AI-integrated systems.

Research is conducted independently and in collaboration with research institutions, academic laboratories, engineering teams, technology partners, and industrial R&D groups.

Focus Areas

Advanced Verification Architectures

Scalable and governance-aware verification methodologies for increasingly heterogeneous systems.

  • ▹Scalable verification frameworks for heterogeneous SoCs and chiplet systems
  • ▹Cross-layer validation coherence (device → circuit → tool → data)
  • ▹Safety- and reliability-driven verification formalization
  • ▹Coverage modeling under architectural complexity
  • ▹Governance models for large multi-site verification environments

Test & 3DIC Methodologies

Architectural evolution of test infrastructures for vertically integrated and heterogeneous systems.

  • ▹3DIC and hierarchical test architectures
  • ▹Advanced repair strategies for heterogeneous integration
  • ▹Cost–quality trade-off modeling
  • ▹Standard-driven infrastructures (IEEE 1838, 1687, 1500)
  • ▹Data-centric test analytics

Advanced Memory Test & Repair

Methodologies addressing high-density SRAM and emerging NVM technologies.

  • ▹BIST optimization for SRAM and emerging NVM technologies
  • ▹Redundancy analysis and yield-aware repair strategies
  • ▹Failure classification in advanced NVM (MRAM, ReRAM, PCM)
  • ▹Integration into hierarchical SoC and 3DIC test flows

Reliability & Lifecycle Modeling

Data-driven modeling of degradation and lifecycle integrity.

  • ▹Predictive reliability modeling across silicon lifecycle
  • ▹Detection of systemic failure patterns
  • ▹Degradation-aware statistical modeling
  • ▹Post-silicon feedback integration into governance frameworks

Applied AI for Engineering Systems

AI-augmented methodologies strengthening validation and decision frameworks.

  • ▹AI-assisted anomaly detection in verification and test flows
  • ▹Intelligent coverage acceleration
  • ▹Data-driven architectural decision support
  • ▹Explainability and traceability in AI-assisted workflows

Standards & Ecosystem Contribution

Research at SIS contributes to the evolution of semiconductor engineering standards and methodological frameworks.

  • ▹Participation in standard working groups
  • ▹Technical position papers
  • ▹Methodological proposals within industry forums
  • ▹Cross-institutional initiatives shaping future verification and test paradigms

Publications & Dissemination

Research outputs are disseminated through:

  • ▹Scientific papers presented at peer-reviewed international conferences
  • ▹Invited talks and expert panels
  • ▹Technical workshops and specialized symposia
  • ▹Executive technical briefings

Publication strategy prioritizes structural impact and methodological advancement over volume.

Research Centers & Laboratory Engagement

SIS collaborates with research centers, academic laboratories, and industrial R&D groups to align methodological research with real semiconductor system challenges.

  • ▹Joint research programs with laboratories and industrial teams
  • ▹Participation in collaborative research centers and consortia
  • ▹Doctoral and post-doctoral co-supervision
  • ▹Technical advisory roles within funded initiatives
  • ▹Contribution to consortium governance and technical steering

This engagement ensures bidirectional knowledge transfer between academic innovation and industrial deployment.

Research Portfolio — By Domain

SIS maintains a structured research portfolio aligned with its technical pillars. Each domain aggregates representative scientific papers, patent filings, and methodological contributions.

Advanced Memory Test & Repair

Scientific papers and patent filings related to memory BIST, redundancy optimization, repair methodologies and advanced NVM reliability modeling will be documented here.

DFT & 3DIC Test Architectures

Research outputs addressing advanced test and heterogeneous integration strategies will be referenced here.

Advanced Verification Architectures

Publications advancing scalable verification coherence will be listed here.

Reliability & Lifecycle Integrity

Research and patent filings related to predictive reliability modeling will be referenced here.

Applied AI for Semiconductor Engineering

Scientific contributions and innovation initiatives in AI-assisted engineering methodologies will be documented here.

Research at SIS ensures that governance, architecture, and engineering decisions are informed by validated, forward-looking technical insight.

Research Collaboration & Technical Exchange

Engage SIS for joint research initiatives, conference collaboration, doctoral co-supervision or strategic technical programs.

Contact SIS