Expertise

Engineering depth structured for strategic impact across verification, test, and reliability.

Strategic Technology Leadership & R&D Governance

Executive-level architectural leadership across semiconductor R&D ecosystems. This role operates at the intersection of engineering depth, long-term platform strategy, and organizational coherence — ensuring that complex technology systems evolve with structural integrity rather than incremental drift.

▹ CTO-level technology vision and architectural arbitration across hardware, software, and data layers

▹ Long-term R&D roadmap definition aligned with business, market, and ecosystem constraints

▹ Leadership of international multi-site engineering organizations (US, Europe, India)

▹ Strategic trade-off arbitration: cost vs. quality, innovation vs. risk, delivery vs. platform sustainability

▹ Executive-level technical due diligence of deep-tech products, IP portfolios, and engineering teams

▹ Structuring and optimization of R&D investment, including public funding mechanisms (e.g., CIR)

▹ Leadership of industry–academic research collaborations and participation in international standardization initiatives

Core Technical Pillars

eda

EDA Product & CAD Platform Architecture

Architecture and scaling of industrial EDA systems and internal CAD infrastructures into robust, production-grade platforms.

▹Definition of scalable EDA architectures for enterprise environments
▹Transformation of internal engineering tools into commercially viable platforms
▹HW/SW co-architecture and toolchain integration strategy
▹Automation, workflow optimization, and infrastructure rationalization
▹Productization strategy bridging engineering capability and market positioning
▹Platform governance to ensure long-term maintainability and evolution

dft

DFT & 3DIC Test Architectures

Strategic definition of advanced Design-for-Test methodologies for increasingly heterogeneous and vertically integrated systems.

▹Architecture of DFT strategies for complex SoCs and chiplet-based systems
▹3DIC test planning and hierarchical test integration
▹Integration of IEEE 1838, 1687, and 1500 standards into scalable test flows
▹Coverage optimization under cost and manufacturing constraints
▹System-level arbitration of quality vs. test time trade-offs
▹Alignment of test architecture with long-term product and reliability strategy

verify

System-Level Verification & Coherence

Ensuring coherence from device physics to data-driven decision layers through structured verification frameworks.

▹Digital verification architecture (UVM, assertions, safety-driven design)
▹Cross-layer coherence: device → circuit → tool → data
▹Integration of hardware and software validation strategies
▹Safety and reliability-oriented verification methodologies
▹Decision intelligence frameworks linking engineering data to executive insight
▹Governance of verification environments for scalability and reuse

Test, Reliability & Safety IP Architecture

Silicon-proven IP design and architecture for test, safety, and reliability — engineered for reuse, configurability, and standards compliance.

▹Design and architecture of digital hardware IPs for advanced semiconductor systems
▹Patented BIST/BISR architectures and scalable repair strategies
▹Safety-oriented verification IPs and integrity-driven building blocks
▹Configurable architectures designed for long-term reuse across product generations
▹Standards-aware integration into SoC, chiplet, and 3DIC environments
▹Documentation and integration guidance to support industrial deployment

memory

Advanced Memory Test & Repair

Embedded memory quality, yield, and repair architectures across SRAM and emerging NVM technologies — bridging methodology, standards, and silicon reality.

▹BIST/BISR architectures for SRAM and emerging NVM (MRAM, FeRAM, and beyond)
▹Repair strategy definition to balance yield, area, and lifecycle robustness
▹Expertise in memory test languages (MTL) and associated industrial adoption
▹Co-creation and contribution to IEEE 1450.6.2 for memory test standardization
▹Yield learning and test optimization during ramp and product maturation
▹Integration guidance for scalable deployment across product families

standards

Standards & Technical Governance

Leadership in international standards definition and adoption — translating research and industrial constraints into interoperable, future-proof specifications.

▹Leadership in definition, adoption, and governance of semiconductor standards
▹Deep involvement across IEEE 1149.x, 1500, 1687, 1838, 1450.6.2, and 3405
▹Research-to-industry translation: turning proposals into implementable norms
▹Interoperability strategy across ecosystems, tools, and supply chains
▹Governance of standards-driven roadmaps and long-term technical alignment
▹Contribution to committees, working groups, and multi-stakeholder consensus

Applied AI for Semiconductor Engineering

Applied AI is positioned as an engineering amplifier — not a product layer — strengthening verification coverage, anomaly detection, and system-level insight without compromising methodological rigor.

▹ AI-assisted anomaly detection in verification and test environments

▹ Coverage analysis acceleration through intelligent pattern recognition

▹ Engineering data mining for early systemic risk detection

▹ Decision-support models for complex architectural trade-offs

▹ Automation of repetitive validation processes under controlled governance

▹ Integration of AI tools into structured engineering workflows

▹ Preservation of explainability and traceability in AI-assisted systems

Request a Strategic Technical Review

For due diligence, roadmap arbitration, or verification/test architecture decisions — engage SIS for a clear, structured technical assessment.

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